Field effect transistors (FETs) have become ubiquitous in modern electronics and are used in switching, amplifying, logic, and memory applications.
In general, a FET has four terminals, which include a source, a gate, a drain, and a body. In many FETs, the body is connected to the source inside the device package. Current flows from the drain to the source in a FET and the amount of current flow is controlled by the voltage applied between the gate and the source. The current flows in a conduction channel, which is generally referred to simply as a channel, and extends between the drain and source of the FET. The amount of current that flows from the drain to the source is proportional to the size of the channel, and the channel size is controlled by the strength of an electric field that is produced when a voltage is applied between the gate and source.
FETs generally have one of two gate structures. The first gate structure provides a gate dielectric to insulate the gate contact from the channel that resides below the gate structure. The gate dielectric is generally an oxide. FETs having this insulated gate structure are generally referred to as a Metal-Oxide-Semiconductor FET (MOSFET). The second gate structure does not incorporate a gate dielectric and places the gate contact substantially directly on the underlying semiconductor. FETs with the second gate structure are referred to as Schottky-gate devices, which include Metal Semiconductor FETS (MESFETs) and High Electronic Mobility Transistors (HEMTs).
FETS may be divided into depletion-mode (d-mode) and enhancement-mode (e-mode) types, depending on whether the FET is normally on or off when no voltage is applied between the gate and source. E-mode FETS are normally off when the gate-to-source voltage is zero. Application of the proper gate-to-source voltage creates a channel between the drain and source and allows current to flow therebetween. As the gate-to-source voltage increases, the channel size increases, and the resultant drain-to-source current increases. In contrast, d-mode FETS are normally on when the gate-to-source voltage is zero. As such, a channel is normally available and current flows between the drain and source when the gate-to-source voltage is zero. Application of the proper gate-to-source voltage reduces the size of the normally available channel between the drain and source and restricts current flow therebetween. As the gate-to-source voltage increases, the channel decreases, and the resultant drain-to-source current decreases.
In many applications, it is beneficial to incorporate both e-mode and d-mode FETs in a circuit design. Given the constant demand for further integration and reduced component sizes, there is a further need to build e-mode and d-mode FETs on a single wafer. Although building these complementary FETS in silicon-based material systems has proven to be relatively easy, the transition to other material subsystems has proven to be more difficult. In particular, little success has been garnered in building complementary FETs in group III-V based material subsystems, and in particular Gallium Arsenide (GaAs) and Indium Phosphide (InP) based material subsystems.
In Silicon-based material subsystems, a pair of complementary MOSFETs may include an N-channel MOSFET, which uses electrons for current conduction, and a P-channel MOSFET, which uses holes for current conduction. The mobility of electrons and holes in Silicon is closely matched. For instance, the low-field mobility of electrons is only two or three times that of the holes. As such, a pair of complementary N- and P-channel MOSFETs can be roughly the same size and have a similar structure while providing complementary operational traits. Unfortunately, there is large difference in electron and hole mobility in group III-V material systems. For instance, the low-field mobility of electrons in GaAs is about 20 times that of the holes. This difference in electron and hole mobility requires the effective gate length of a P-channel device to be sized much smaller than the gate length of an N-channel device to achieve similar performance. As such, the size and structure of the respective complementary devices that provide similar performance are quite different. When used in a complementary fashion, the geometry of the gate structure for the P-channel device is significantly different than that of the N-channel device. These differences present difficulties in layout and manufacturing as well as impact overall performance of these devices when they are connected in a complementary fashion.
Another issue with group III-V material systems has been forming an acceptable gate dielectric for MOSFETs. Although forming an oxide for a gate dielectric in Silicon has always been relatively easy; forming effective oxides in group III-V material systems has proven to be difficult. When an oxide for the gate dielectric is created for group III-V material systems, the interface properties between the oxide and the underlying semiconductor material tends to perform poorly. In particular, the interface traps and interface defects tend to be high, and the interface tends to absorb impurities at an excessive rate.
Accordingly, there is a need for an efficient and effective technique to form complementary FETs in a group III-V material system that does not require the complementary devices to be disparately sized. There is a further need for an effective oxide to use as a gate dielectric when providing complementary FETs in a group III-V material subsystem.